As integration of elements in integrated circuits (IC) increases, line widths and geometries for semiconductor devices are reduced. Accordingly, resistance of a gate and a source/drain region of a MOS transistor made by conventional techniques are relatively high. In conventional techniques, an interlayer dielectric (ILD) layer and an etch stop layer are formed on a patterned substrate for isolation and over-etching. Then, the ILD layer and the etch stop layer are etched using an etchant to form an opening (surrounded by a sidewall of the ILD layer and the etch stop layer) for exposing a contact area such as the source/drain region, and a metal silicide layer can be formed on the contact area through the opening for reducing the resistance.
In the operation of forming the metal silicide layer, the opening is required to be cleaned first. In conventional techniques, a liner is formed conformal to the opening, and then a sputter etching operation (such as using an inert gas) and an SPM (Sulfuric Acid-Hydrogen Peroxide Mixture) operation (such as using H2SO4 and H2O2 solution) are performed in sequence. The liner protects the sidewall from being damaged by the sputter etching operation and the SPM operation. However, the liner is not perfectly adhesive to the sidewall and has a poor surface, such that an interface between the ILD layer and the etch stop layer is etched by the H2SO4 and H2O2 solution at SPM operation. In some conditions, a metal gate (MG) of the patterned substrate is also partially or entirely removed (which is also referred to as MG missing) by the H2SO4 and H2O2 solution etching, thus impacting the IC performance and yield.